This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-359762, filed Nov. 27, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor apparatus, particularly to a semiconductor apparatus in which a MOSFET is formed on an Si pillar of a longitudinal and laterally three-layered structure of NPN (or PNP), and to a structure suitable for a power switching device which requires a low on-resistance/high breakdown voltage.
2. Description of the Related Art
A power switching device utilizing a MOSFET is required to have a low on-resistance/high breakdown voltage. In a power MOSFET having a conventional planar structure, however, when the on-resistance is lowered, the breakdown voltage is also lowered. When the breakdown voltage is raised, the on-resistance is raised. The device has an opposite relation.
That is, in the power MOSFET of the planar structure, a MOS structure is formed on the upper surface of an Nxe2x88x92 epitaxial layer formed, for example, on an N+ substrate, and a current path extending to the MOSFET on the upper surface from a back surface of the substrate via the Nxe2x88x92 epitaxial layer is formed.
Therefore, a resistance during an on operation of the MOSFET (on-resistance) depends on a thickness of the Nxe2x88x92 epitaxial layer. Moreover, since a depletion layer extends in the Nxe2x88x92 epitaxial layer, the breakdown voltage is determined by the thickness of the Nxe2x88x92 epitaxial layer.
As described above, the current path is the same as a region for maintaining the breakdown voltage. Therefore, when the thickness of the Nxe2x88x92 epitaxial layer is set to be large for enhancement of the breakdown voltage, the on-resistance increases. Conversely, when the Nxe2x88x92 epitaxial layer is formed to be thin and the on-resistance is lowered, the breakdown voltage also decreases. Such opposite relation exists, and it is difficult to satisfy both conditions.
In order to wipe away the relation opposite to the relation of the low on-resistance/high breakdown voltage, and obtain the low on-resistance/high breakdown voltage in the power MOSFET of the conventional planar structure, for example, a MOSFET (cool MOS; trademark of Siemens Co., Germany) having a super junction structure is known, for example, by xe2x80x9cCool MOS-a new milestone in high voltage Power MOSxe2x80x9d by L. Lorenz, G. Deboy (Document 1) (e.g., Jpn. Pat. Appln. KOKAI Publication No. 7-7154).
In the power MOSFET of the super junction structure, as shown in FIG. 1, an N+ pillar layer 71 constituting the current path and a P+ pillar layer 72 for maintaining the reverse breakdown voltage between drain and source are formed in a depth direction (vertical direction), respectively.
According to the structure, the on-resistance depends on an impurity concentration of the N+ pillar layer 71. Moreover, the breakdown voltage extends the depletion layer in a lateral direction, and is therefore determined by an impurity concentration and width of the P+ pillar layer 72. As a result, it is possible to secure an equal reverse breakdown voltage (e.g., 600V) between drain and source and to reduce the on-resistance to about ⅓ to xc2xc with respect to the power MOSFET of the conventional planar structure.
Additionally, a manufacturing process of the MOSFET disclosed in Document 1 is complicated, because epitaxial growth of silicon, patterning, and ion implantation need to be repeated a plurality of times (six times in FIG. 1). With such very long process, cost and time are required. It is feared that a manufacturing cost largely rises.
A method of ion-implanting N or P type impurities into each side surface of a striped trench formed in a semiconductor substrate and forming a longitudinal N or P pillar layer has also been proposed (U.S. Pat. No. 6,040,600). However, also in this method, two ion implantation steps are necessary for forming the N and P pillar layers for one element of MOSFET, and further there is a restriction that only a MOSFET having a stripe pattern as a planar form can be formed.
Therefore, there has been a demand for establishment of a new structure of the power MOSFET which is easy in manufacturing, high in breakdown voltage, and low in on-resistance.
According to a first aspect of the present invention, there is provided a semiconductor apparatus comprising:
a semiconductor substrate of a first conductivity type having a first and a second main surface;
a plurality of element isolation regions formed to have a predetermined depth DT from the first main surface of the semiconductor substrate, and formed by filling a plurality of trenches with an insulator;
a laterally three-layered pillar formed among the plurality of element isolation regions with a width WP and in a meshed planar shape, comprising a first and a second pillar layer of the first conductivity type which contact two adjacent element isolation regions out of the plurality of element isolation regions over a depth direction, respectively, and a third pillar layer of a second conductivity type formed between the first and the second pillar layer, and having a relation of 3.75xe2x89xa6DT/WPxe2x89xa660 between the width WP of the three-layered pillar and the depth DT of the element isolation region;
a base region of the second conductivity type formed on an upper surface of the third pillar layer of the second conductivity type;
a source region of the first conductivity type selectively formed on the upper surface of the base region;
a gate electrode formed on the base region between the source region and an upper surface of the first or the second pillar layer in an insulating manner; and
a drain layer of the first conductivity type formed on the second main surface of the semiconductor substrate, and contacting a lower surface of the three-layered pillar.
According to a second aspect of the present invention, there is provided a semiconductor apparatus comprising:
a semiconductor substrate of a first conductivity type having a first and a second main surface;
a plurality of element isolation regions formed to have a predetermined depth DT from the first main surface of the semiconductor substrate, and formed by filling a plurality of trenches with an insulator;
a laterally three-layered pillar formed among the plurality of element isolation regions with a width WP and in a meshed planar shape, so as to have a plurality of openings having a minimum opening width WTmin, comprising a first and a second pillar layer of the first conductivity type which contact two adjacent element isolation regions out of the plurality of element isolation regions over a depth direction, respectively, comprising a third pillar layer of a second conductivity type formed between the first and the second pillar layer, and having a relation of 5.5xe2x89xa6DT/WTminxe2x89xa614.3 between the opening width WTmin of the three-layered pillar and the depth DT of the element isolation region;
a base region of the second conductivity type formed on an upper surface of the third pillar layer of the second conductivity type;
a source region of the first conductivity type selectively formed on an upper surface of the base region;
a gate electrode formed on the base region between the source region and an upper surface of the first or the second pillar layer in an insulating manner; and
a drain layer of the first conductivity type formed on the second main surface of the semiconductor substrate, and contacting a lower surface of the three-layered pillar.
According to a third aspect of the present invention, there is provided a semiconductor apparatus comprising:
a semiconductor substrate of a first conductivity type having a first and a second main surface;
a plurality of element isolation regions formed to have a predetermined depth DT from the first main surface of the semiconductor substrate, and formed by filling a plurality of trenches with an insulator;
a laterally three-layered pillar formed among the plurality of element isolation regions with a width WP and in a meshed planar shape so as to have a plurality of openings having a minimum opening width WTmin, comprising a first and a second pillar layer of the first conductivity type which contact two adjacent element isolation regions out of the plurality of element isolation regions over a depth direction, respectively, and comprising a third pillar layer of a second conductivity type formed between the first and the second pillar layer;
a base region of the second conductivity type formed on an upper surface of the third pillar layer of the second conductivity type;
a source region of the first conductivity type selectively formed on an upper surface of the base region;
a gate electrode formed on the base region between the source region and an upper surface of the first or the second pillar layer in an insulating manner; and
a drain layer of the first conductivity type formed on the second main surface of the semiconductor substrate, and contacting a lower surface of the three-layered pillar,
wherein the plurality of element isolation regions include an edge termination isolation region surrounding a region with the three-layered pillar formed therein, and a relation with the minimum opening width WTmin of the meshed three-layered pillar satisfies WTEminxe2x89xa7WTmin, assuming that a minimum opening width of one of the plurality of trenches corresponding to the edge termination isolation region is WTEmin.